An image sensor may be a semiconductor device to convert an optical image into an electrical signal. An image sensor may be a charge coupled device (CCD), where individual metaloxide-silicon (MOS) capacitors may be located adjacent each other and may store charge carriers and may further transfer them. Alternatively, an image sensor may be a CMOS (complementary MOS) image sensor, which may adopt a switching manner. A CMOS device may include as many MOS transistors as a number of pixels. A CMOS device may include, as peripheral circuits, a control circuit and a signal processing circuit, and may sequentially detect outputs using such circuits.
A CMOS image sensor may implement images by forming a photodiode and a MOS transistor in a unit pixel and detecting the signals in the switching manner.
In a related art process of manufacturing a CMOS image sensor, an NPN element may be manufactured by applying a CMOS process to an epi-layer.
FIG. 1 is a drawing illustrating a related art horizontal type NPN bipolar junction transistor element and FIG. 2 is a drawing illustrating a cross section of the horizontal type NPN bipolar junction transistor element shown in FIG. 1.
Referring to FIGS. 1 and 2, the horizontal type NPN bipolar junction transistor element may include shallow trench isolation (STI) area 160, which may be a device isolating area, on P-type semiconductor substrate 100 and may include P-well 112 and N-well 110.
N-type emitter E, P-type base B, and N-type collector C may be formed in P-well 112, and a N-type guard ring (N-ISO) may be formed in N-well 110 and may space P-well 112 from the peripheral thereof.
STI area 160 may be formed between emitter E and base B and between collector C and the N-type guard ring (N-ISO) and may partition each area.
Each upper layer of emitter E, base B, and collector C area may be formed with emitter contact area 126 and collector contact area 130, where a high concentration of N-type ionss may be implanted, and base contact area 128, where P-type ionss may be implanted. An upper layer of the N-type guard ring (N-ISO) area may be formed with a guard ring contact area where a high concentration of N-type ions may be implanted.
Emitter contact area 126, collector contact area 130, base contact area 128, and the N-type guard ring (N-ISO) area may each contact metal electrodes 133a, 133b, 133c, and 133d. 
The P-well may be formed with the emitter and the collector together, which may allow for the electrons implanted from the N-type emitter E to flow to the N-type collector C, and may form horizontal collector current IC in a normal active mode.
However, the ratio of base current IB to collector current IC in the bipolar junction transistor element BJT, that is, IC/IB may be referred to as a common emitter current gain (beta), and may be an important specification that may determine DC performance of the element.
There may be a problem that the current gain of the horizontal type bipolar junction transistor (BJT) element in the related art may be small because the base layer may be wide. For example, the current gain of a horizontal type bipolar junction transistor (BJT) element may be smaller than that of a vertical type bipolar junction transistor element in which current may flow vertically.
Moreover, since the current flow may be non-uniform in view of a element structure, it may be difficult to expect and model current.